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<span id="NDS32-Options"></span><div class="header">
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<hr>
<span id="NDS32-Options-1"></span><h4 class="subsection">3.19.33 NDS32 Options</h4>
<span id="index-NDS32-Options"></span>

<p>These options are defined for NDS32 implementations:
</p>
<dl compact="compact">
<dd>
<span id="index-mbig_002dendian-9"></span>
</dd>
<dt><code>-mbig-endian</code></dt>
<dd><p>Generate code in big-endian mode.
</p>
<span id="index-mlittle_002dendian-9"></span>
</dd>
<dt><code>-mlittle-endian</code></dt>
<dd><p>Generate code in little-endian mode.
</p>
<span id="index-mreduced_002dregs"></span>
</dd>
<dt><code>-mreduced-regs</code></dt>
<dd><p>Use reduced-set registers for register allocation.
</p>
<span id="index-mfull_002dregs"></span>
</dd>
<dt><code>-mfull-regs</code></dt>
<dd><p>Use full-set registers for register allocation.
</p>
<span id="index-mcmov"></span>
</dd>
<dt><code>-mcmov</code></dt>
<dd><p>Generate conditional move instructions.
</p>
<span id="index-mno_002dcmov"></span>
</dd>
<dt><code>-mno-cmov</code></dt>
<dd><p>Do not generate conditional move instructions.
</p>
<span id="index-mext_002dperf"></span>
</dd>
<dt><code>-mext-perf</code></dt>
<dd><p>Generate performance extension instructions.
</p>
<span id="index-mno_002dext_002dperf"></span>
</dd>
<dt><code>-mno-ext-perf</code></dt>
<dd><p>Do not generate performance extension instructions.
</p>
<span id="index-mext_002dperf2"></span>
</dd>
<dt><code>-mext-perf2</code></dt>
<dd><p>Generate performance extension 2 instructions.
</p>
<span id="index-mno_002dext_002dperf2"></span>
</dd>
<dt><code>-mno-ext-perf2</code></dt>
<dd><p>Do not generate performance extension 2 instructions.
</p>
<span id="index-mext_002dstring"></span>
</dd>
<dt><code>-mext-string</code></dt>
<dd><p>Generate string extension instructions.
</p>
<span id="index-mno_002dext_002dstring"></span>
</dd>
<dt><code>-mno-ext-string</code></dt>
<dd><p>Do not generate string extension instructions.
</p>
<span id="index-mv3push"></span>
</dd>
<dt><code>-mv3push</code></dt>
<dd><p>Generate v3 push25/pop25 instructions.
</p>
<span id="index-mno_002dv3push"></span>
</dd>
<dt><code>-mno-v3push</code></dt>
<dd><p>Do not generate v3 push25/pop25 instructions.
</p>
<span id="index-m16_002dbit-1"></span>
</dd>
<dt><code>-m16-bit</code></dt>
<dd><p>Generate 16-bit instructions.
</p>
<span id="index-mno_002d16_002dbit"></span>
</dd>
<dt><code>-mno-16-bit</code></dt>
<dd><p>Do not generate 16-bit instructions.
</p>
<span id="index-misr_002dvector_002dsize"></span>
</dd>
<dt><code>-misr-vector-size=<var>num</var></code></dt>
<dd><p>Specify the size of each interrupt vector, which must be 4 or 16.
</p>
<span id="index-mcache_002dblock_002dsize"></span>
</dd>
<dt><code>-mcache-block-size=<var>num</var></code></dt>
<dd><p>Specify the size of each cache block,
which must be a power of 2 between 4 and 512.
</p>
<span id="index-march-10"></span>
</dd>
<dt><code>-march=<var>arch</var></code></dt>
<dd><p>Specify the name of the target architecture.
</p>
<span id="index-mcmodel"></span>
</dd>
<dt><code>-mcmodel=<var>code-model</var></code></dt>
<dd><p>Set the code model to one of
</p><dl compact="compact">
<dt>&lsquo;<samp>small</samp>&rsquo;</dt>
<dd><p>All the data and read-only data segments must be within 512KB addressing space.
The text segment must be within 16MB addressing space.
</p></dd>
<dt>&lsquo;<samp>medium</samp>&rsquo;</dt>
<dd><p>The data segment must be within 512KB while the read-only data segment can be
within 4GB addressing space.  The text segment should be still within 16MB
addressing space.
</p></dd>
<dt>&lsquo;<samp>large</samp>&rsquo;</dt>
<dd><p>All the text and data segments can be within 4GB addressing space.
</p></dd>
</dl>

<span id="index-mctor_002ddtor"></span>
</dd>
<dt><code>-mctor-dtor</code></dt>
<dd><p>Enable constructor/destructor feature.
</p>
<span id="index-mrelax-4"></span>
</dd>
<dt><code>-mrelax</code></dt>
<dd><p>Guide linker to relax instructions.
</p>
</dd>
</dl>

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